Power controlling method for semiconductor storage device and semiconductor storage device employing same

ABSTRACT

A method for controlling power for a semiconductor storage device and the semiconductor storage device are provided which enable power consumption to be greatly reduced in a standby state. The power control method uses an ultra-low power consumption mode in which power control can be exerted in the standby state. In the ultra-low power consumption mode, a burst self-refresh state, power-OFF state, and power-ON state are provided. In the burst self-refresh state, memory cells are refreshed in a centralized manner. In the power-OFF state, an internal power source circuit can be partially turned OFF. In the power-ON state, internal power sources having been partially turned OFF are turned ON. Therefore, it is possible to greatly reduce power consumption in the standby state.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method for controlling powerfor a semiconductor storage device having a memory cell which must berefreshed to maintain data and the semiconductor storage deviceemploying the method for controlling power.

[0003] The present application claims priority of Japanese PatentApplication No. 2001-256913 filed on Aug. 27, 2001, which is herebyincorporated by reference.

[0004] 2. Description of the Related Art

[0005]FIG. 13 is a block diagram showing an example of configurations ofa conventional semiconductor storage device having a memory cell whichmust be refreshed to maintain data. The conventional semiconductorstorage device is a DRAM (Dynamic Random Access Memory) having a storagecapacity of 64 Mbits and is made up of four banks and having a number ofrefresh processes denoting a number of rows in each of memory cellarrays 11 ₁ to 11 ₄ activated by one time refresh process being4096(=2¹²). The conventional semiconductor storage device chieflyincludes four pieces of banks 1 ₁ to 1 ₄, column decoder groups 2 ₁to 2₄, row decoder groups 3 ₁ to 3 ₄, an input buffer 4, an output buffer 5,a multiplexer (MUX) 6, a command decoder 7, a row column address buffer8, a refresh counter 9, and a self-refresh circuit 10.

[0006] Each of the banks 1 ₁ to 1 ₄ includes each of the memory cellarrays 11 ₁ to 11 ₄ and each of sense amplifiers/input and output buses(SA-IOB) 12 ₁ to 12 ₄. Each of the memory cell arrays 11 ₁ to 11 ₄ has astorage capacity of 16 Mbits in which a plurality of pieces of memorycells is arranged in a matrix form. Each of sense amplifiers (SAs)making up each of the SA-IOB 12 ₁ to 12 ₄ detects data read from amemory cell on a column of corresponding memory cell arrays 11 ₁ to 11 ₄being selected by a row decoder making up the corresponding row decodergroups 3 ₁ to 3 ₄ to a bit line and amplifies the detected data. Each ofthe input/output buses (IOBs) making up each of the SA-IOBs 12 ₁ to 12₄, while being connected to a global input/output bus 13, at a time ofreading data, transmits data detected and amplified by each of thecorresponding SAs to the global input/output bus 13 while, at a time ofwriting data, transmits the data transmitted by the global input/outputbus 13 to a memory cell selected out of the corresponding memory cellarrays 11 ₁ to 11 ₄.

[0007] Each of the column decoder groups 2 ₁ to 2 ₄ is mounted on eachof the banks 1 ₁ to 1 ₄ and has a plurality of column decoders. Each ofthe column decoders operates to decode a column address fed from a rowcolumn address buffer 8 and outputs a plurality of column selectionswitching signals used to put each of the SAs being connected tocorresponding bit lines of each of memory cell arrays 11 ₁ to 11 ₄ intoa selection state. Each of the row decoder groups 3 ₁ to 3 ₄ is mountedon each of the banks 1 ₁ to 1 ₄ and has a plurality of row decoders.Each of the row decoders decodes a row address fed from the row columnaddress buffer 8 and puts a corresponding word line of each of thememory cell arrays 11 ₁ to 11 ₄ into the selection state.

[0008] The input buffer 4 being connected commonly to the banks 1 ₁ to 1₄ amplifies and buffers data being input a data input/output terminal DQand then feeds it to the MUX 6. The output buffer 5 being connectedcommonly to the banks 1 ₁ to 1 ₄ amplifies and buffers data fed from theMUX 6 and outputs sequentially it from the data input/output terminalDQ. The MUX 6 feeds data supplied through the global input and outputbus 13 from the IOBs making up the SA-IOB 12 ₁ to 12 ₄ to the outputbuffer 5 and data fed from the input buffer 4 through the globalinput/output bus 13 to the IOBs making up SA-IOB 12 ₁ to 12 ₄.

[0009] The command decoder 7, when a clock enable signal CKE fed from anexternal is changed from its high to low level, decodes a chip selectsignal /Cs, row address strobe signal /RAS, column address strobe signal/CAS, and write enable signal /WE fed in synchronization with a clockCLK fed from an external and, if it is judged that operations are in aself-refresh mode (entry), produces a high-level self-refresh startsignal SRT and feeds the row column address buffer 8 and theself-refresh circuit 10. The self-refresh start signal SRT is used toinstruct a self-refresh process to be started. Also, the command decoder7 produces a row activated signal φ RAS based on a self-refresh signal φSRF supplied from the self-refresh circuit 10 and feeds it to a rowcolumn address buffer 8. The self-refresh signal φ SRF is an originalsignal from which the row activated signal φ RAS is produced and is usedto set a basic period for the self-refresh process. The row activatedsignal φ RAS is a basic signal used to activate row-based componentssuch as the row decoder groups 3 ₁ to 3 ₄ or a like. Moreover, the clockenable signal CKE is active high while the chip select signal /CS, rowaddress strobe signal /RAS, column address strobe signal /CAS, and writeenable signal /WE are all active low.

[0010] The row column address buffer 8, while an ordinary operation isbeing performed, produces a column address and a row address based on anaddress AD fed from an external and the row address is fed to aplurality of row decoders making up each of the row decoder groups 3 ₁to 3 ₄ with timing when a row activated signal φ RAS is fed from acommand decoder 7. Also, the row column address buffer 8, when aself-refresh start signal SRT is fed from the command decoder 7 at atime of the self-refresh process, based on a counter value RCT suppliedfrom the refresh counter 9, produces a row address for the self-refreshprocess and, with timing when a row activated signal φ RAS supplied fromthe command decoder 7 is fed, feeds the row address to the plurality ofrow decoders making up each of the row decoder groups 3 ₁ to 3 ₄. In therefresh counter 9, at the time of a self-refresh process, its countervalue RCT is updated and the updated counter value RCT is fed to the rowcolumn address buffer 8. The self-refresh circuit 10, based on ahigh-level self-refresh start signal SRT supplied from the commanddecoder 7, produces a self-refresh signal φ SRF in a period of a clockproduced by an oscillator (not shown) mounted therein and feeds it tothe command decoder 7.

[0011] Next, internal operations of the semiconductor storage devicehaving configurations described above to be performed at a time of theself-refresh process will be described by referring to a timing chartshown in FIG. 14. First, the clock enable signal CKE, as shown in FIG.14 (2), remains high in an initial state before time t₁ and the clockCLK changes to be low in synchronization with a rise of a clock CLK atthe time t₂ (see FIG. 14(1)). That is, in the initial state before thetime t₁, an internal state ST of the conventional semiconductor storagedevice is an idle state IST in which no operation is performed, as shownin FIG. 14(4).

[0012] In such the initial state, the clock enable signal CKE (see FIG.14(1)) changes to be low in synchronization with a rise of a clock CLKat the time t₂ as shown in FIG. 14(2) and, as shown in FIG. 14(3), acommand SRC, one of a command CMD, used to instruct setting of aself-refresh mode is fed. The command SRC is fed when, for example, alow-level chip selector signal /CS, low-level row address strobe signal/RAS, low-level column address strobe signal /CAS and high-level writeenable signal /WE are supplied in synchronization with the clock CLK.This makes the command decoder 7 decode the low-level chip select signal/CS, low-level row address strobe signal /RAS, low level column addressstrobe signal /CAS and high-level write enable signal /WE and judgesthat operations are set to be in a self-refresh mode. Therefore, thecommand decoder 7 produces a high-level self-refresh start signal SRTshown in FIG. 14(5) and feeds it to the self-refresh circuit 10.

[0013] This causes the internal state ST of the conventionalsemiconductor storage device to be changed from its idle state IST toits self-refresh state SRST, as shown in FIG. 14(4). That is, theself-refresh circuit 10, based on a high-level self-refresh start signalSRT fed from the command decoder 7, in a period of a clock produced bythe oscillator mounted therein, produces a self-refresh signal φ SRFshown in FIG. 14(6) and feeds it to the command decoder 7. This causesthe command decoder 7 to produce, based on a self-refresh signal φ SRFfed from the self-refresh circuit 10, a row activated signal φ RAS shownin FIG. 14(7) and feeds it to the row column address buffer 8.Therefore, the row column address buffer 8, when a self-refresh startsignal SRT is fed from the command decoder 7, based on a counter valueRCT supplied from the refresh counter 9, produces a row address to beused for the self-refresh process and feeds it to each of a plurality ofrow decoders making up each of the row decoder groups 3 ₁ to 3 ₄ withtiming when a row activated signal φ RAS is fed from the command decoder7. Thereafter, in the conventional semiconductor storage device, arefresh process is performed at equal intervals on all word lines (4096cycles) in a period of a clock (hereinafter referred to be a refreshperiod T_(R)) produced by an oscillator mounted within the self-refreshcircuit 10. Since the conventional semiconductor storage device is aDRAM (Dynamic Random Access Memory) having a number of refresh processesdenoting a number of rows of a memory cell array activated by one timerefresh process being 4096(=2¹²), so long as the refresh process is notperformed, if time during which data is not lost (being referred to as areal refreshing capability t_(REF)) is 64 msec, the refresh period T_(R)is set, in advance, to be 15.6 μsec (FIG. 14(6))-On the other hand, ifthe real refreshing capability t_(REF) is 128 msec, the refresh periodT_(R) is set to be 31.2 μsec.

[0014] Next, to exit the self-refresh mode, for example, at the time t₃,as shown in FIG. 14(2), regardless of a rising edge of the clock CLK(see FIG. 14(1)) at the time t₃, a clock enable signal CKE is changedfrom its low to high level. This causes the command decoder 7 to changea self-refresh start signal SRT from its high to low level and feeds itto the self-refresh circuit 10. Therefore, the self-refresh circuit 10,based on a low-level self-refresh start signal SRT fed from the commanddecoder 7, as shown in FIG. 14(6), stops production of a self-refreshsignal φ SRF. As a result, the command decoder 7, since a self-refreshsignal φ SRF is not fed from the self-refresh circuit 10, as shown inFIG. 14(7), stops the production of a row activated signal φ RAS. Byoperations described above, the internal state ST of the conventionalsemiconductor storage device, as shown in FIG. 14(4), changes from itsself-refresh state SRST to its idle state IST. Moreover, when the clockenable signal CKE is changed from its low to high level, if a refreshprocess is performed, after the refresh process has finished, theinternal state ST of the conventional storage device changes from itsself-refresh state SRST to its idle state IST.

[0015] In a self-refresh mode, in a standby state where a system such asa computer or a like, in which DRAMs are mounted, is not accessed froman external, data being stored in a memory cell is periodically andautomatically held. Therefore, in the self-refresh mode, refreshprocesses are not directly related to operations of systems, it is thusdesirous that power consumption is made as small as possible. In recentyears in particular, portable electronic devices are widely used and, inthe semiconductor storage device being mounted in portable electronicdevices, more reduction in power consumption is required and aspecification of current consumption becomes more rigorous(conventionally being specified to be about 1 mA. However, it is nowabout 100 μA ). Here, the portable electronic device includesnotebook-type, palm-type, and pocket-type computers, or a like, a PDA(Personal Digital Assistance), portable cellular phone, PHS (PersonalHandy-phone System), or a like.

[0016] Next, a reason why power consumption in the portable electronicdevice has to be reduced will be described. In portable electronicdevices, power is supplied from a battery, a dry cell, or a like and apower source voltage of the portable electronic device is lower thanthat of a stationary type electronic device whose power is supplied froma commercial power source. Therefore, a power source voltage employed inthe semiconductor storage device being mounted in portable electronicdevices is made lower which, as a result, causes a threshold voltage ofa transistor making up peripheral devices such as an input buffer 4 oroutput buffer 5 to be made lower. A leak current (sub-threshold leakcurrent) occurring in a standby state in such the peripheral circuitstends to increase due to such lowering in the threshold voltage of thetransistor making up the peripheral circuits.

[0017] Moreover, as described above, in the semiconductor storage devicebeing mounted on portable electronic devices, due to rigorousspecifications of current consumption, a current being consumed at atime of refreshing is reduced and, as a result, not only a minute leakcurrent but also the sub-threshold leak current occurring due todefective processes in each of the memory cells may not be negligible.However, in the conventional semiconductor storage device, in itsself-refresh mode, as described above, only a thing that is done thereinis to perform a periodical refresh process at a refresh period T_(R)having been set in advance according to the real refreshing capabilityt_(REF) in the semiconductor storage device. Therefore, in the aboveconventional semiconductor device, a data maintaining current isdetermined by the real refreshing capability t_(REF) and an alternatingcurrent cannot be reduced and rigorous specifications of currentconsumption are not met. Moreover, a direct current such as a leakcurrent, minute leak current, or a like that tend to increase cannot bereduced.

SUMMARY OF THE INVENTION

[0018] In view of the above, it is an object of the present invention toprovide a method for controlling power for a semiconductor storagedevice and the semiconductor storage device which enable powerconsumption to be greatly reduced in a standby state.

[0019] According to a first aspect of the present invention, there isprovided a method for controlling power for a semiconductor storagedevice having a memory cell which must be refreshed to maintain data,including:

[0020] a step of employing an ultra-low power consumption mode in whichpower control is exerted in a standby state and in which a centralizedrefresh state, power-OFF state, and power-ON state are provided, and

[0021] wherein the memory cell is refreshed in a centralized manner inthe centralized refresh state, an internal power source circuit ispartially turned OFF in the power-OFF state, and the internal powersource circuit having been partially turned OFF is turned ON in thepower-ON state.

[0022] In the foregoing, a preferable mode is one wherein, in theultra-low power consumption mode, an error correcting circuit encodestate and an error correcting circuit decode state are provided andwherein, in the error correcting circuit encode state, an arithmeticoperation is performed on parity bits by the error correcting circuit torestore the memory cell whose maintaining (holding) characteristics aredeteriorated and wherein, in the error correcting encode state, an errorcorrection is made by the error correcting circuit based on results fromthe arithmetic operations.

[0023] Also, a preferable mode is one wherein the error correctingcircuit operates in synchronization with a clock produced internally orfed from an external.

[0024] Also, a preferable mode is one wherein a state signal indicatingthat the semiconductor storage device is internally put in the ultra-lowpower consumption mode is output to an external.

[0025] Also, a preferable mode is one wherein the semiconductor storagedevice is configured to operate in a self-refresh mode such that thememory cell is periodically and automatically refreshed.

[0026] Also, a preferable mode is one wherein, in the centralizedrefresh state, the refresh process is performed on the memory cell in aperiod being shorter than that being corresponded to a maintainingcharacteristic of the memory cell.

[0027] Also, a preferable mode is one wherein, wherein, in the power-OFFstate, all power sources other than paired poles in the internal powersource circuit are turned OFF.

[0028] Also, a preferable mode is one wherein, in the power-OFF state,leak paths of peripheral circuits of a memory cell array made up of aplurality of the memory cells are interrupted.

[0029] Also, a preferable mode is one wherein transition to thecentralized refresh state occurs when instructions for the semiconductorstorage device to be put in the ultra-low power consumption mode areprovided and then transition from the centralized refresh state to thepower-OFF state, from the power-OFF state to the power-ON state, andfrom the power-ON state to the centralized state are repeated.

[0030] Also, a preferable mode is one wherein, in the ultra-low powerconsumption mode, if the semiconductor storage device is put in thecentralized refresh state when instructions for exiting the ultra-lowpower consumption mode are provided, transition occurs to a self-refreshstate in which the memory cell is refreshed in a period corresponding toa maintaining characteristic of the memory cell.

[0031] Also, a preferable mode is one wherein, in the ultra-low powerconsumption mode, if the semiconductor storage device is put in thepower-OFF state when instructions for exiting the ultra-low powerconsumption mode are provided, transition occurs to a self-refresh statein which the memory cell is refreshed in a period corresponding to amaintaining characteristic of the memory cell.

[0032] Also, a preferable mode is one wherein, when instructions for thesemiconductor storage device to be put in the ultra-low powerconsumption mode are provided, transition to the error correctingcircuit encode state and to the centralized refresh state sequentiallyoccur and, until instructions for exiting the ultra-low powerconsumption mode are provided, transition from the centralized refreshstate to the power-OFF state, from the power-OFF state to the power-ONstate, and from the power-ON state to the centralized refresh state arerepeated.

[0033] Also, a preferable mode is one wherein, when instructions for thesemiconductor storage device to be put in the ultra-low powerconsumption mode are provided, transition to the error correcting encodestate, to the power-OFF state, and to the centralized refresh statesequentially occurs and, until instructions for exiting the ultra-lowpower consumption mode are provided, transition from the centralizedrefresh state to the power-OFF state, from the power-OFF state to thepower-ON state, and from the power-ON state to the centralized refreshstate are repeated.

[0034] Also, a preferable mode is one wherein, in the ultra-low powerconsumption mode, if the semiconductor storage device is put in thecentralized refresh state when the ultra-low power consumption modeexits, transition to the error correcting circuit decode state occursand then transition occurs to a self-refresh state in which the memorycell is refreshed in a period corresponding to a maintainingcharacteristic of the memory cell.

[0035] Also, a preferable mode is one wherein, in the ultra-low powerconsumption mode, if the semiconductor storage device is put in thepower-OFF state when instructions for exiting the ultra-low powerconsumption mode are provided, transition to the power-ON state and tothe error correcting circuit decode state sequentially occurs and thentransition occurs to a self-refresh state in which the memory cell isrefreshed in a period corresponding to a maintaining characteristic ofthe memory cell.

[0036] Also, a preferable mode is one wherein, in the ultra-low powerconsumption mode, if the semiconductor storage device is put in theerror correcting circuit encode state when instructions for exiting theultra-low power consumption mode are provided, after termination of theerror correcting circuit encode state, transition occurs to aself-refresh state in which the memory cell is refreshed in a periodcorresponding to a maintaining characteristic of the memory cell,

[0037] Also, a preferable mode is one, wherein instructions are providedto put the semiconductor storage device into the ultra-low powerconsumption mode by a first change occurring in a specified signal fedfrom an external and to exit the ultra-low power consumption mode by asecond change occurring in the specified signal.

[0038] Also, a preferable mode is one wherein, after instructions havebeen provided for exiting the ultra-low power consumption mode,instructions are provided for transition of an internal state of thesemiconductor storage device to an idle state where no operation isperformed again by the second change occurring in the specified signal.

[0039] Also, a preferable mode is one wherein, after having thespecified signal produce the second change in order to give instructionsfor exiting the ultra-low power consumption mode, when maximum time ormore required for error corrections in the error correcting circuitdecode state has elapsed, the second change is produced in the specifiedsignal used to give instructions for transition of an internal state ofthe semiconductor storage device to the idle state.

[0040] According to a second aspect of the present invention, there isprovided a semiconductor storage device having a memory cell which mustbe refreshed to maintain data, including:

[0041] a self-refresh executing unit to refresh the memory cell;

[0042] an internal power source circuit to provide power to each ofcomponents; and

[0043] a controller, when instructions are provided for operations in anultra-low power consumption mode in order to exert power control in astandby state, to have the self-refresh executing unit execute refreshoperations in a centralized refresh state in which a centralized refreshprocess is performed on the memory cell, in a power-OFF state in whichthe internal power source circuit is partially turned OFF, and in apower-ON state in which the internal power source circuit having beenpartially turned OFF is turned ON.

[0044] In the foregoing, a preferable mode is one that where includes anerror correcting circuit used to perform arithmetic operations on paritybits to restore the memory cell whose maintaining characteristics aredeteriorated and to make error corrections based on results from thearithmetic operations and wherein the controller executes operations inan error correcting circuit encode state to have the error correctingcircuit perform the arithmetic operations and in an error correctingcircuit decode state to have the error correcting circuit make the errorcorrection.

[0045] Also, a preferable mode is one wherein the error correctingcircuit operates in synchronization with a clock occurring internally orbeing fed from an external.

[0046] Also, a preferable mode is one wherein the controller outputs astate signal indicating that the semiconductor storage device isinternally put in the ultra-low power consumption mode.

[0047] Also, a preferable mode is one wherein a self-refresh mode isused which is able to perform the refresh operations periodically andautomatically.

[0048] Also, a preferable mode is one wherein the controller has, in thecentralized refresh state, the refresh executing unit perform therefresh process in a period being shorter than that corresponding to amaintaining characteristic of the memory cell.

[0049] Also, a preferable mode is one wherein the controller, in thepower-OFF state, turns OFF all power sources other than paired poles inthe internal power source circuit.

[0050] Also, a preferable mode is one wherein the controller, in thepower-OFF state, interrupts a leak path of peripheral circuits of amemory array made up of a plurality of the memory cells.

[0051] Also, a preferable mode is one wherein the controller, wheninstructions are provided for operations in the ultra-low powerconsumption mode, changes an internal state of the semiconductor storagedevice to the centralized refresh state and, until instructions forexiting the ultra-low power consumption mode are provided, repeatstransition from the centralized refresh state to the power-OFF state,from the power-OFF state to the power-ON state, and from the power-ONstate to the centralized refresh state.

[0052] Also, a preferable mode is one wherein the controller, in theultra-low power consumption state, if the semiconductor storage deviceis put in the centralized refresh state when instructions for exitingthe ultra-low power consumption state are provided, induces occurrenceof transition of an internal state of the semiconductor storage deviceto a self-refresh state in which a refresh process is performed on thememory cell in a period corresponding to a maintaining characteristic ofthe memory cell.

[0053] Also, a preferable mode is one wherein the controller, in theultra-low power consumption mode, if the semiconductor storage device isput in the power-OFF state when instructions for exiting the ultra-lowpower consumption mode are provided, changes an internal state of thesemiconductor storage device to the power-ON state and then inducesoccurrence of transition to a self-refresh state in which a refreshprocess is performed on the memory cell in a period corresponding to amaintaining characteristic of the memory cell.

[0054] Also, a preferable mode is one wherein the controller, wheninstructions for operations in the ultra-low power consumption areprovided, sequentially changes an internal state of the semiconductorstorage device to the error correcting circuit encode state and to thecentralized refresh state and, until instructions for exiting theultra-low power consumption are provided, repeats transition from thecentralized refresh state to the power-OFF state, from the power-OFFstate to the power-ON state, and from the power-ON state to thecentralized refresh state.

[0055] Also, a preferable mode is one wherein the controller, wheninstructions for operations in the ultra-low power consumption areprovided, sequentially changes an internal state of the semiconductorstorage device to the error correcting circuit encode state, to thepower-OFF state, and to the centralized refresh state and, untilinstructions for exiting the ultra-low power consumption are provided,repeats transition from the centralized refresh state to the power-OFFstate, from the power-OFF state to the power-ON state, and from thepower-ON state to the centralized refresh state.

[0056] Also, a preferable mode is one wherein the controller, in theultra-low power consumption mode, if the semiconductor storage device isput in the centralized refresh state when instructions for exiting theultra-low power consumption mode are provided, changes an internal stateof the semiconductor storage device to the error correcting circuitdecode state and then induces occurrence of transition of an internalstate of the semiconductor storage device to a self-refresh state inwhich a refresh process is performed on the memory cell in a periodcorresponding to a maintaining characteristic of the memory cell.

[0057] Also, a preferable mode is one wherein the controller, in theultra-low power consumption mode, if the semiconductor storage device isput in the power-OFF state when instructions for exiting the ultra-lowpower consumption mode are provided, changes an internal state of thesemiconductor storage device to the power-ON state and to the errorcorrecting circuit decode state and then induces occurrence oftransition of an internal state of the semiconductor storage device to aself-refresh state in which a refresh process is performed on the memorycell in a period corresponding to a maintaining characteristic of thememory cell.

[0058] Also, a preferable mode is one wherein the controller, in theultra-low power consumption mode, if the semiconductor storage device isput in the error correcting circuit encode state when instructions forexiting the ultra-low power consumption mode are provided and after theerror correcting circuit encode state has been terminated, inducesoccurrence of transition of an internal state of the semiconductorstorage device to a self-refresh state in which a refresh process isperformed on the memory cell in a period corresponding to a maintainingcharacteristic of the memory cell.

[0059] Also, a preferable mode is one wherein instructions foroperations in the ultra-low power consumption mode are provided by afirst change occurring in the specified signal and instructions forexiting the ultra-low power consumption mode are provided by a secondchange occurring in the specified signal.

[0060] Also, a preferable mode is one wherein, after the ultra-low powerconsumption mode has been exited, instructions for transition of aninternal state of the semiconductor storage device into an idle state inwhich no operation is performed are provided by the second change againoccurring in the specified signal.

[0061] Furthermore, a preferable mode is one wherein, after the secondchange has occurred in the specified signal which are used to provideinstructions for exiting the ultra-low power consumption mode and whenmaximum time or more required for error correction in the errorcorrecting circuit decode state has elapsed, the second change isproduced in the specified signal to provide instructions for transfer ofan internal state of the semiconductor storage device to the idle state.

[0062] With the above configurations, an ultra-low power consumptionmode is employed in which power control can be exerted in a standbystate. In the ultra-low power consumption mode, a centralized refreshstate, power-OFF state, and power-ON state are provided. In thecentralized refresh state, memory cells are refreshed in a centralizedmanner. In the power-OFF state, internal power source circuit can bepartially turned OFF. In the power-ON state, the internal power sourcehaving been partially turned OFF is turned ON. Therefore, it is possibleto greatly reduce power consumption in a standby state.

BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The above and other objects, advantages, and features of thepresent invention will be more apparent from the following descriptiontaken in conjunction with the accompanying drawings in which:

[0064]FIG. 1 is a schematic block diagram showing configurations of asemiconductor storage device employing a method for controlling powerfor the semiconductor storage device of an embodiment of the presentinvention;

[0065]FIGS. 2A and 2B are diagrams showing configurations of a maincomponent of a peripheral circuit according to the embodiment of thepresent invention; wherein FIG. 2A is a circuit diagram showing oneexample of configurations of a main component of a row decoder and FIG.2 is a circuit diagram showing one example of configurations of a maincomponent of a random logic section according to the embodiment of thepresent invention;

[0066]FIG. 3 is a timing chart explaining internal operations performedwhen an ultra-low power consumption mode exits in a burst self-refreshstate after the semiconductor storage device has been put in theultra-low power consumption mode according to the embodiment of thepresent invention;

[0067]FIG. 4 is a state transition diagram for explaining internaloperations performed when the ultra-low power consumption mode exits ina burst self-refresh state after the semiconductor storage device hasbeen put in the ultra-low power consumption mode according to theembodiment of the present invention;

[0068]FIG. 5 is a timing chart explaining internal operations performedwhen the ultra-low power consumption mode exits in a power-OFF stateafter the semiconductor storage device has been put in the ultra-lowpower consumption mode according to the embodiment of the presentinvention;

[0069]FIG. 6 is a state transition diagram explaining internaloperations performed when the ultra-low power consumption mode exits inthe power-OFF state after the semiconductor storage device has been putin the ultra-low power consumption mode according to the embodiment ofthe present invention;

[0070]FIG. 7 is a timing chart explaining internal operations performedwhen the ultra-low power consumption mode exits in an EEC-encoding stateafter the semiconductor storage device has been put in the ultra-lowpower consumption mode according to the embodiment of the presentinvention;

[0071]FIG. 8 is a state transition diagram for explaining internaloperations performed when the ultra-low power consumption mode exits inthe EEC encoding state after the semiconductor storage device has beenput in the ultra-low power consumption mode according to the embodimentof the present invention;

[0072]FIG. 9 is a timing chart for explaining an external specificationof the ultra-low power consumption mode of the semiconductor storagedevice according to the embodiment of the present invention;

[0073]FIG. 10 is a timing chart for explaining an external specificationof an ordinary self-refresh mode of the semiconductor storage deviceaccording to the embodiment of the present invention;

[0074]FIG. 11 is a graph for explaining an effect obtained by the methodfor controlling power for the semiconductor storage device of theembodiment of the present invention;

[0075]FIG. 12 is a timing chart explaining an external specification foran ultra-low power consumption mode in the semiconductor storage devicein a modified embodiment of the present invention;

[0076]FIG. 13 is a block diagram showing an example of configurations ofa conventional semiconductor storage device; and

[0077]FIG. 14 is a timing chart illustrating internal operationsperformed while the conventional semiconductor storage device isrefreshed.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0078] Best modes of carrying out the present invention will bedescribed in further detail using various embodiments with reference tothe accompanying drawings.

[0079] In the present invention, by changing an internal state of asemiconductor storage device to a state obtained by combining an ECC(error correction circuit) encode state EEST, a burst self-refresh stateBSST, a power-OFF state PFST, a power-ON state PNST, an ECC decode stateEDST, and an ordinary self-refresh state SRST, great reduction in powerconsumption in the internal power source circuit in a stand-by state isachieved. Here, a mode in which the ECC encode state EEST, the burstself-refresh state BSST, the power-OFF state PFST, the power-ON statePNST, and the ECC decode state EDST are provided in combination toachieve great reduction in power consumption is called an “ultra-lowpower consumption mode”.

[0080] The ECC encode state EEST represents a state in which reading andwriting of data at a usual time which can be performed without a hitchby using an ECC circuit formed within a semiconductor chip and in whichan arithmetic calculation of parity bits used to correct an error of abit (refresh defective bit) being stored in a memory cell whosemaintaining characteristics deteriorate and writing of a parity regioninto the memory cell are performed, The burst self-refresh state BSSTrepresent a state in which a refresh process is collectively performedin a comparatively short refresh period T_(R) (hereafter being called a“burst self-refresh”) unlike an ordinary self-refresh in which a refreshprocess is performed in a disperse manner. For example, when the refreshperiod T_(R) for the ordinary self-refresh is set to be 15.6 μsecaccording to real refreshing capability t_(REF) (64 msec), the refreshperiod T_(R) for the burst self-refresh is set to be several μsec. Byperforming the burst self-refresh, power-OFF time of the internal powersource circuit is extended and, as a result, an amount of a directcurrent is greatly reduced.

[0081] The power-OFF state PFST represents a state in which currentconsumption in the internal power source circuit is reduced by turningOFF all power sources except paired poles making up the internal powersource circuit during a non-operation period acquired by extending therefresh time in the ECC encode state EEST and by employing a peripheralcircuit standby current reduction (SCRC) method by which a leak path ofperipheral circuits of a memory cell array is interrupted, various kindsof leak currents such as the sub-threshold leak currents describedabove, minute leak currents, or a like are reduced. The power-ON statePNST represents a state in which, in order to perform the burstself-refresh in the subsequent burst self-refresh state BSST, theinternal power source circuit is turned ON and operations using theperipheral circuit SCRC method are cancelled. The ECC decode state EDSTrepresents a state in which an error of a refresh defective bit on whicharithmetic calculations are performed is corrected. The self-refreshstate SRST represents a state in which an ordinary self-refreshdescribed in the conventional technology is performed, that is,refreshing in a memory cell is carried out in a refresh period T_(R)according to a maintaining characteristic.

[0082] In the FCC encode state EEST and ECC decode state EDST, byextending apparent refresh time up to a maximum that can be assured bythe characteristic, an amount of an alternating current can be reduced.For example, in the case of the semiconductor storage device whose realrefreshing capability t_(REF) being 64 msec, the apparent realrefreshing capability is extended by about 1 sec. Moreover, byrepetition of the above burst self-refresh state BSST, the power-OFFstate PFST, and the power-ON state PNST, an amount of a direct currentis reduced. By operating the semiconductor storage device in theultra-low power consumption mode, an average amount of currentconsumption at a time of maintaining data can be reduced to aboutone-tenth of the level in the conventional art.

Embodiment

[0083]FIG. 1 is a schematic block diagram for showing configurations ofa semiconductor storage device employing a method for controlling powerfor the semiconductor storage device employed in an embodiment of thepresent invention. In FIG. 1, same reference numbers are assigned tocorresponding parts having same functions as in FIG. 13 and theirdescriptions are omitted accordingly. In the semiconductor storagedevice shown in FIG. 1, instead of a command decoder 7 and aself-refresh circuit 10, a command decoder 21 and a self-refresh circuit22 are newly mounted. As shown in FIG. 1, an ECC controller 23, an ECC24, an internal clock generating circuit 25, a timer 26, an internalpower source circuit 27, and an OR gate 28 are newly added. Moreover,though the internal power source circuit is provided in thesemiconductor storage device, too, since an internal voltage V_(DDI) isalways fed to each of components while operations are in a self-refreshmode, no special explanation is provided. A real refreshing capabilityof the semiconductor storage device of the embodiment is set to be 64msec.

[0084] In the command decoder 21, in addition to a function of aconventional command decoder, an ECC mode decoder 31 and a self-modedecoder 32 are additionally added. The command decoder 21, based on aself-refresh signal φ SRF supplied from the self-refresh circuit 22,produces a row activated signal φ RAS and feeds it to a row columnaddress buffer 8. The ECC mode decoder 31, when a clock enable signalCKE fed from an external changes from its high to low level, decodes achip select signal /CS, a row address strobe signal /RAS, a columnaddress strobe signal /CAS, and a write enable signal /WE, all of whichare fed in synchronization with a clock CLK supplied from the externaland, when it is judged that setting is made so as to operate thesemiconductor storage device in an ultra-low power consumption mode,produces a high-level encode start signal ENST, then feeds it to the ECCcontroller 23 and sets the ultra-low power consumption flag SLPF showingthat the setting is made so as to operate the semiconductor storagedevice in the ultra-low power consumption mode and an encode flagshowing that the ECC 24 is performing its encoding process. Then, whenan encoder terminating signal ENED indicating that encoding process hasterminated in the ECC 24 is supplied from the ECC controller 23, the ECCmode decoder 31 resets the encode flag.

[0085] Moreover, the ECC mode decoder 31, when an instruction forexiting the ultra-low power consumption mode is provided from anexternal by a change of the clock enable signal CKE from its high to lowlevel, resets the above ultra-low power consumption flag SLPF. At thispoint, the ECC mode decoder 31, depending on whether the encode flag hasbeen set or reset, judges whether a state having just existed till nowis an ultra-low power consumption mode and the ECC 24 has terminated itsencoding operations or whether the state having just existed till now isan ordinary self-refresh mode in which the ECC 24 has not yet performedits encoding operations. Then, if operations are in the ultra-low powerconsumption mode and the ECC 24 has terminated its encoding operations,the ECC mode decoder 31 produces a high-level decode start signal DEST,then feeds it to the ECC controller 23 and sets a decode flag indicatingthat the ECC 24 is under decoding. Next, when a decode terminatingsignal DEED indicating that decoding in the ECC 24 has terminated is fedfrom the ECC controller 23, the ECC mode decoder 31 resets a decodeflag.

[0086] Moreover, the ECC mode decoder 31, if the ultra-low powerconsumption flag SLPF is set when an “internal power source ON signal”GON, being fed from the internal power source circuit 27, and informingthat a potential at an internal specified portion has reached aspecified potential and that the internal power source has been turnedON, is changed from its low to high level, makes high a secondself-refresh start signal SRT₂. On the other hand, when the “internalpower source ON signal” GON changes from its low to high level, if theultra-low. power consumption flag SLPF is set, since the secondself-refresh start signal SRT₂ goes high, the ECC mode decoder 31produces a high-level decode start signal DEST, then feeds it to the ECCcontroller 23 and sets a decode flags.

[0087] The self-mode decoder 32, when a clock enable signal CKE fed fromthe external is changed from its high to low level, decodes the chipselect signal /CS, the row address strobe signal /RAS, the columnaddress strobe signal /CAS, and the write enable signal /WE, all ofwhich are fed in synchronization with the clock CLK supplied from theexternal and, when it is judged that setting is made so as to operatethe semiconductor storage device not in the ultra-low power consumptionmode but in the ordinary self-refresh mode, produces a high-level firstself-refresh start signal SRT₁ and feeds it to the self-refresh circuit22 and the OR gate 28. Also, the self-mode decoder 32, when a clockenable signal CKE fed from the external is changed from its high to lowlevel, decodes the chip select signal /CS, the row address strobe signal/RAS, the column address strobe signal /CAS and the write enable signal/WE, all of which are fed in synchronization with the clock CLK fed fromthe external and, when setting is made so as to operate thesemiconductor storage device in the ultra-low power consumption mode,sets the ultra-low power consumption flag SLPF indicating thatoperations are in the ultra-low power consumption. Moreover, theself-mode decoder 32, when an instruction for exiting the ultra-lowpower consumption mode is fed due to a change of a clock enable signalCKE fed from the external from its high to low level, resets theultra-low power consumption mode and, regardless of levels of the firstand second self-refresh start signals SRT₁ and SRT₂, resets the firstand second self-refresh start signal SRT₁ and SRT₂ to become at a lowlevel.

[0088] Furthermore, the self-mode decoder 32, when an encode terminatingsignal ENED is fed from the ECC controller 23 and if the above ultra-lowpower consumption flag SLPF is set, produces a high-level secondself-refresh start signal SRT₂ and feeds it to the self-refresh circuit22, the OR gate 28, and the ECC mode decoder 31. Similarly, theself-mode decoder 32, when an “internal power source ON signal” GON fedfrom the internal power source circuit 27 is changed from its low tohigh level and if the ultra-low power consumption flag SLPF is set,produces a second high-level self-refresh start signal SRT₂ and feeds itto the self-refresh circuit 22, the OR gate 28 and the ECC mode decoder31. Moreover, the self-mode decoder 32, when the decode terminatingsignal DEED is fed, produces a first high-level self-refresh startsignal SRT₁ and feeds it to the self-refresh circuit 22 and the OR gate28.

[0089] The self-refresh circuit 22 changes, based on first and secondhigh-level self-refresh start signals SRT₁ and SRT₂ fed from theself-mode decoder 32, an oscillation frequency of the clock produced byan oscillator mounted therein and produces a self-refresh signal φ SRFand feeds it to the command decoder 21. The self-refresh circuit 22,when the first high-level self-refresh start signal SRT₁ is fed, setsthe oscillation frequency of a clock produced by the oscillator so thatthe refresh period T_(R) becomes 15.6 μsec and, when the secondhigh-level self-refresh start signal SRT₂ is fed, the oscillationfrequency of the clock produced by the oscillator so that the refreshperiod T_(R) becomes several microseconds.

[0090] Also, the self-refresh circuit 22, when a value of a countermounted therein becomes 4096 by termination of the burst self-refreshprocess on all word lines in all memory cell arrays 11 ₁ to 11 ₄,produces a high-level self-refresh terminating signal SRED indicatingthat the burst self-refresh process has terminated and feeds it to theself-mode decoder 32 and the timer 26. Moreover, the self-refreshcircuit 22, based on the self-refresh terminating signal SRED, producesa high-level “internal power source OFF signal” GOFF to instruct theinternal power source circuit 27 to be turned OFF. Also, theself-refresh circuit 22, based on an “internal power source OFFterminating signal” PEND, being fed from the timer 26, indicating thattime (being called “internal power source OFF time”) required to turnOFF the internal power source circuit 27 has elapsed, changes the“internal power source OFF signal” PEND from its high to low level toactivate the internal power source circuit 27 and feeds it to theinternal power source circuit 27.

[0091] The ECC controller 23, based on a high-level encode start signalENST fed from the ECC mode decoder 31, produces an internal command, anaddress AD, and an encode flag ENC used to control reading and writingoperations during encoding in synchronization with an internal clockCLK_(IN) being supplied from the internal clock generating circuit 25and feeds the internal command and the address AD to the command decoder21 and the encode flag ENC to the ECC 24. Here, the internal command ismade up of the chip select signal /CS, the row address strobe signal/RAS, the column address strobe signal /CA and the write enable signal/WE. The command decoder 21 takes in an internal command by a risingedge occurring when the internal clock CLK_(IN) is changed from its lowto high level. The ECC controller 23, when parity calculation to beperformed on all memory cells making up the memory cell arrays 11 ₁ to11 ₄ and writing of a parity region into each of the memory cells areterminated in the ECC 24, feeds an encoder terminating signal ENED tothe ECC mode decoder 31. Moreover, the ECC controller 23, based on ahigh-level decode start signal DEST fed from the ECC mode decoder 31 andin synchronization with an internal clock CLK_(IN), produces theinternal command, the address AD, and the decode flag DEC each beingused to control reading and writing operations in the decode and feedsthe internal command and the address AD to the command decoder 21 andencode flag ENC to the ECC 24. Then, the ECC controller 23, when thedecoding instructed as above in the ECC 24 is terminated, feeds a decodeterminating signal DEED to the ECC mode decoder 31 and self-mode decoder32.

[0092] The ECC 24, based on an encode flag ENC fed from the ECCcontroller 23 and in synchronization with an internal clock CLK_(IN) fedfrom the internal clock generating circuit 25, makes an access through aMUX 6 to each of banks 1 ₁ to 1 ₄, and performs arithmetic calculationof parity bits used to correct errors of a refresh defective bit andwriting of a parity region into the memory cell. Also, the ECC 24, basedon a decode flag DEC fed from the ECC controller 23, makes an accessthrough the MUX 6 to each of the banks 1 ₁ to 1 ₄ in synchronizationwith an internal clock CLK_(IN) and corrects an error of a refreshdefective bit having performed arithmetic calculations of parity bits.Error correcting capability of the ECC 24, if a storage capacity of thesemiconductor storage device is, for example, 64 Mbits, may be about1,000 to 10,000 bits. The internal clock generating circuit 25 producesan internal clock CLK_(IN) to be used in the ECC controller 23 and theECC 24. The timer 26, based on a high-level self-refresh terminatingsignal SRED fed from the self-refresh circuit 22, starts a measurementof time of the internal power source OFF time which is set in advanceand is programmed by using a fuse or a like and, when the internal powersource OFF time has elapsed, feeds an “internal power source OFFterminating signal” PEND indicating its lapse to the self-refreshcircuit 22. The timer 26, while the internal power source OFF time isbeing measured, if the ultra-low power consumption flag SLPF fed fromthe self-mode decoder 32 by changes of the clock enable signal CKE fromits low to high level is reset, stops the measurement of the internalpower source OFF time and feeds a high-level “internal power source OFFsignal” PEND to the self-refresh circuit 22.

[0093] The internal power source circuit 27 feeds various voltagesoccurring within each component of the semiconductor storage deviceincluding, for example, a word line potential V_(PP), a bit linepotential V_(ARY), a potential being one half of the bit line potential,a paired pole potential V_(PLT), a peripheral circuit potential V_(PER),a memory cell section substrate potential V_(BB) and a high-levelactivated signal ACT used to supply the above internal voltage orexternal voltage V_(DDE) to column decoders making up column decodergroups 2 ₁ to 2 ₄, row decoders making up row decoder groups 3 ₁ to 3 ₄or a peripheral circuit (FIGS. 2A and 2B) made up of random logicsections or a like. The internal power source circuit 27, based on ahigh-level “internal power source OFF signal” GOFF, stops a supply of aninternal voltage to the semiconductor storage device and changes anactivated signal ACT from its high to low level and then feeds it to theabove peripheral circuit. Moreover, the internal power source circuit27, when the “internal power source OFF signal” GOFF fed from theself-refresh circuit 22 is changed from its high to low level, starts asupply of an internal voltage to the semiconductor storage device andchanges the above activated signal ACT to its low to high level andfeeds it to the above peripheral circuit.

[0094]FIGS. 2A and 2B are diagrams showing configurations of maincomponents of the peripheral circuit of the embodiment of the presentinvention. FIG. 2A shows an example of configurations of the maincomponent of a row decoder 41. In the row decoder 41, at a later stageof a decoding section 42 used to decode a row address, inverters 43 ₁ to43 _(n) each being made up of P-channel MOS transistors and N-channelMOS transistors are provided as an output section and each of outputterminals of the inverters 43 ₁ to 43 _(n) (“n” representing a naturalnumber) is connected to each of corresponding word lines WL₁ to WL_(n)of the corresponding memory cell array 11 ₁, 11 ₂, 11 ₃, or 11 ₄. Toeach of sources of the P-channel MOS transistors making up each ofinverters 43 ₁ to 43 _(m), a drain of the P-channel MOS transistors 44making up a power source interrupting section is connected. To a sourceof a MOS transistor 44 is applied an external voltage V_(DDE) and to itsgate is applied an activated signal ACT through an inverter 45 making upa power supply interrupting section. Therefore, at a time of a power-OFFstate PFST, when the activated signal ACT changes from its high to lowlevel, since the MOS transistor 44 is turned OFF, production of asub-threshold leak current of the row decoder 41 is inhibited FIG. 2Bshows an example of configurations of main components of a random logicsection 51.

[0095] In the random logic section 51, “m” pieces of inverters 52 ₁ to52 _(m) (m is a natural number) each being made up of P-channel MOStransistors and N-channel MOS transistors are cascaded. To each ofsources of the P-channel MOS transistors making up each of inverters 52₁ to 52 _(m), a drain of the P-channel MOS transistors 53 making up apower source interrupting section is connected. To a source of the MOStransistor 53 is applied an external voltage V_(DDE) and to its gate isapplied an activated signal ACT through an inverter 54 making up thepower source interrupting section. Therefore, when the activated signalACT is changed from its high to low level at a time of power-OFF statePFST, since the MOS transistor 53 is turned OFF, occurrence of thesub-threshold leak current in the random logic section 51 is inhibited.

[0096] The internal power source circuit 27, since it takes much timefor example, about 200 μsec) to supply, in a stable manner, an internalvoltage having a specified value after operations have been started,monitors a potential at which it takes most time to reach the potentialhaving the specified value described above, out of potentials applied toeach component, and then detects that the potential has reached thathaving the specified value and supplies a high-level “internal powersource ON signal” GON to the ECC mode decoder 31 and the self-modedecoder 32. The potential to be supplied by the internal power sourcecircuit 27, as described above, generally includes a word line potentialV_(PP), a bit line potential V_(ARY), a potential being one half of thatof a bit line, a paired pole potential V_(PLT), a peripheral circuitpotential V_(PER), and a memory cell portion substrate potential V_(BB)or a like. Of them, a potential at which it takes most time to reach thepotential having the specified value is the word line potential V_(PP)or the memory cell portion substrate potential V_(BB). The above time isdetermined by current supplying capability of the internal power sourcecircuit 27 and by load capacity existing therein. The current supplyingcapability of the internal power source circuit 27 is ordinarilydetermined so that the potential reaches that having the specified valueat the time when 100 μsec have elapsed in an initializing sequence at atime of design. For example, if there exists a large parasitic capacitybetween the memory section substrate potential V_(BB) and the word linepotential V_(PP), it is necessary that a supply of the word linepotential V_(PP) is started after having the memory section substratepotential V_(BB) reach a specified potential value, the word linepotential V_(PP) is a potential at which most time is required to reachthe specified potential value. A reason why the potential is applied insuch order as described above is to avoid a risk of breaking data beingstored in a memory cell occurring when the potential V_(BB) of thememory cell section substrate is made positive by having the word linepotential V_(PP) reach a specified potential value. The OR gate 85operates to OR a first refresh start signal with a second refresh signaland applies its calculation result to the row column address buffer 8.

[0097] Operations of the semiconductor storage device having theconfigurations described above will be explained. First, internaloperations being performed at an ultra-low power consumption mode willbe described by referring to a timing chart shown in FIGS. 3, 4, and 7and to a state transition diagram shown in FIGS. 4, 6, and 8.

[0098] (1) Case in which, the semiconductor storage device, having beenset to an ultra-low power consumption mode, exits it at a burstself-refresh state “BSST” (see FIGS. 3 and 4).

[0099] Here, let it be assumed that a clock enable signal CKE, as shownin FIG. 3(3), remains high in an initial state before a time t₁ and itchanges to become low in synchronization with a rise of a clock CLK (seeFIG. 3(1)) at a time t₂. That is, the internal state ST of thesemiconductor storage device of the embodiment is, as shown in FIG. 3(5)and FIG. 4, an idle state IST in which no operation is performed at theidle time.

[0100] In such the initial state, the clock enable signal CKE, as shownin FIG. 3(3), changes to become low in synchronization with a risk ofthe clock CLK (see FIG. 3(1)) at the time t₂ and, at the same time, acommand SPC being one of the commands CMP is supplied, as shown in FIG.3(4), to issue an instruction for setting the ultra-low powerconsumption mode. The command SPC is supplied when, for example, a lowchip selector signal /CS, a high-level row address strobe signal /RAS, ahigh column address strobe signal /CAS and a low level write enablesignal /WE are fed in synchronization with the clock CLK. This causesthe internal state ST of the semiconductor storage device of theembodiment to be changed from its idle state IST to the ECC encode stateEEST as shown in FIG. 3(5) and FIG. 4. The ECC mode decoder 31 andself-mode decoder 32 making up the command decoder 21 decode a low-levelchip select signal /CS, a high-level row address strobe signal /RAS, ahigh column address strobe signal /CA, and a low-level write-enablesignal /WE, all of which are the command SPC, and judges that thesemiconductor storage device is in an ultra-low power consumption mode.Therefore, the ECC mode decoder 31 produces a high-level encode startsignal ENST and feeds it to the ECC controller 23 and sets an ultra-lowpower consumption flag SLPF (see FIG. 3(19)) and an encoder flag. On theother hand, the self-mode decoder 32 sets an ultra-low power consumptionflag SLPF.

[0101] The ECC controller 23, based on a high-level encode start signalENST, in synchronization with an internal clock CLK_(IN) shown in FIG.3(2), produces an internal command, address AD, and encode flag ENC andfeeds the internal command and address AD to the command decoder 21 andthe encode flag ENC to the ECC 24. This causes the ECC 24 to access thebanks 1 ₁ to 1 ₄ through the MUX 6, based on the encode command ENC andin synchronization with the internal clock CLK_(IN) shown in FIG. 3(2)and activates appropriate word lines of each of memory cell arrays 11 ₁to 11 ₄ and performs arithmetic calculations on parity bits used tocorrect a refresh defective bit and writing of a parity region to amemory cell. Then, the ECC controller 23, when the arithmeticcalculation of parity bits on all memory cells making up each of memorycell arrays 11 ₁ to 11 ₄ and writing of a parity region to a memory cellare completed in the ECC 24, feeds a high-level encode terminatingsignal END shown in FIG. 3(17) to the ECC mode decoder 31 and self-modedecoder 32. Therefore, the ECC mode decoder 31, when the encodeterminating signal ENED is fed from the ECC controller 23, resets anencode flag. On the other hand, the self-mode decoder 32, when theencode terminating signal ENED is fed from the ECC controller 23, sincethe ultra-low power consumption flag is set in this case, produces ahigh-level second self-refresh start signal SRT₂ shown in FIG. 3(18) andfeeds it to the self-refresh circuit 22, OR gate 28 and ECC mode decoder31.

[0102] This causes the internal state ST of the semiconductor storagedevice of the embodiment to be changed from the ECC encode state EEST tothe burst self-refresh state BSST. That is, the self-refresh circuit 22,since a high-level second self-refresh start signal SRT₂ is fed, afterhaving set an oscillation frequency of a clock produced by theoscillator so that a refresh period T_(R) is several μsec, produces aself-refresh signal φ SRF shown in FIG. 3(9) and feeds it to the rowcolumn address buffer 8 and the command decoder 21. This causes thecommand decoder 21 to produce a row activated signal φ RAS as shown inFIG. 4(10) and feeds it to the row column address buffer 8.

[0103] Therefore, the row column address buffer 8, when a secondself-refresh start signal SRT₂ is fed through the OR gate 28, based on acounter value RCT fed from the refresh counter 9, produces a row addressfor a burst self-refresh process and then feeds it, with timing when therow activated signal φ RAS is fed, to a plurality of row decoders makingup each of row decoder groups 3 ₁ to 3 ₄. Thereafter, in thesemiconductor storage device of the embodiment, refreshing operationsare performed at equal intervals on all word lines (4096 cycles) in arefresh period T_(R) of several μsec.

[0104] Then, the self-refresh circuit 22, when a counter value providedtherein becomes 4096 by completion of the burst self-refresh process tobe performed on all word lines of all the memory cells array 11 ₁ to 11₄, produces a high-level self-refresh terminating signal SRED shown inFIG. 3(11) and feeds it to the self-mode decoder 32 and timer 26.Moreover, the self-refresh circuit 22, based on a self-refreshterminating signal SRED, produces a high-level “internal power sourceOFF signal” GOFF and feeds it to the internal power source circuit 27.

[0105] This causes the internal state ST of the semiconductor storagedevice of the embodiment to be changed from the burst self-refresh stateBSST to the power-OFF state PFST. That is, the internal power sourcecircuit 27, based on a high-level “internal power source OFF signal”GOFF, stops a supply of an internal voltage to the semiconductor storagedevice and, by changing an activated signal ACT from its high to lowlevel, an internal voltage being fed to peripheral circuits constructedof column decoders making up column decoder groups 2 ₁ to 2 ₄, rowdecoders making up row decoder groups 3 ₁ to 3 ₄, random logic sections,or a like is shut off from an external voltage V_(DDE). As a result, asshown in FIG. 3(15), since the internal voltage is lowered, powerconsumption in the internal power source circuit 27 is reduced and aleak current flowing from its internal power source circuit 27 (a shortproviding low resistance and a sub-threshold leak current) is alsoreduced. Moreover, in the peripheral circuits, the sub-threshold leakcurrent is interrupted. On the other hand, the timer 26, based on ahigh-level self-refresh terminating signal SRED, starts measurements ofthe internal power source OFF time. Then, if the internal power sourceoff time has elapsed, the timer 26 feeds a high-level “internal powersource OFF signal” PEND shown in FIG. 3(12) to the self-refresh circuit22. Therefore, the self-refresh circuit 22, based on the high-level“internal power source OFF signal” PEND, to activate the internal powersource circuit 27, as shown in FIG. 3(13), by having changed the“internal power source OFF signal” GOFF from its high to low level,feeds the “internal power source OFF signal” GOFF to the internal powersource circuit 27.

[0106] This causes the internal state ST of the semiconductor storagedevice of the embodiment to be changed from its power-OFF state PFST toits power-ON state PNST. That is, the internal power source circuit 27,since the “internal power source OFF signal” GOFF is changed from itshigh to low level, as shown in FIG. 3(15), starts a supply of theinternal voltage to each of components of the semiconductor storagedevice. The internal power source circuit 27, when having detected thata potential being monitored (in this case, word line potential V_(PP))reaches a specified value of a potential, feeds the high-level “internalpower source ON signal” GON shown in FIG. 3(14) to the ECC mode decoder31 and self-mode decoder 32. Therefore, the self-decoder 32, since the“internal power source ON signal” GON is changed from its low to highlevel and since the ultra-low power consumption flag is set, produces ahigh-level second self-refresh start signal SRT₂ and feeds it to theself-refresh circuit 22, the OR gate 28, and ECC mode decoder 31. On theother hand, the ECC mode decoder 31, though its “internal power sourceON signal” GON is changed from its low to high level, since theultra-low power consumption flag SLPF is set, no operation is performed.

[0107] This causes an internal state ST of the semiconductor storagedevice of the embodiment to be changed to a power-ON state PNST to aburst self-refresh state BSST. Thereafter, until a clock enable signalCKE shown in FIG. 3(3) is changed from its low to high level, theinternal state ST of the semiconductor storage device of the embodiment,as shown in FIG. 4 repeats transition from its burst self-refresh stateBSST to its power-OFF state PFST, from its power-OFF state PFST to itspower-ON state PNST, and from its power-ON state PNST to its burstself-refresh state BSST.

[0108] Then, as shown in FIG. 3(3), let it be assumed that, at the timet₃ when the internal state ST of the semiconductor storage device of theembodiment is a burst self-refresh state BSST, to exit the ultra-lowpower consumption mode, the clock enable signal CKE is changed from itslow to high level. This causes the self-mode decoder 32 to reset theultra-low power consumption flag and, as shown in FIG. 3(8), to change asecond self-refresh start signal SRT₂ from its high to low level andthen feeds it to the self-refresh circuit 22, OR gate, and ECC modedecoder 31. Moreover, the ECC mode decoder 31, in response to a changeof the clock enable signal CKE from its high to low level, as shown inFIG. 3(19), resets the ultra-low power consumption flag. Therefore, theECC mode decoder 31, since the ultra-low power consumption flag SLPF isreset in this case and the encode flag is reset, judges that a statehaving existed till then is an ultra-low power consumption state and ina state where the ECC 24 has terminated its encoding operations. The ECCmode decoder 31 produces a high-level decode start signal DEST shown inFIG. 3(16), feeds it to the ECC controller 23 and sets the decode flag.

[0109] This causes the internal state ST of the semiconductor storagedevice of the embodiment to be changed and, as shown in FIG. 3(5) andFIG. 4, transition from its burst self-refresh state BSST to its ECCdecode EDST occurs. That is, the self-refresh circuit 22, based on thelow-level second self-refresh start signal SRT₂, stops the production ofthe self-refresh signal φ SRF. As a result, the command decoder 21,since the self-refresh signal φ SRF is not fed from the self-refreshcircuit 22, stops the production of the row activated signal φ RSA. Onthe other hand, the ECC controller 23, based on a high-level decodestart signal DEST, in synchronization of an internal clock CLK_(IN)shown in FIG. 3(2), produces an internal command used to control readingand writing operations while the decoding is performed, an address AD,and a decode flag DEC and supplies the internal command and the addressAD to the command decoder 21 and the encode flag ENC to the ECC 24. Thiscauses the ECC 24 to access the banks 1 ₁ to 1 ₄ through the MUX 6 insynchronization with an internal clock CLK_(IN) shown in FIG. 3(2) andto make a correction to errors in a refresh failure bit on whicharithmetic calculation of parity bits has been performed. Then, the ECCcontroller 23, when the instructed decoding operation has beenterminated in the ECC 24, feeds a high-level decode terminating signalDEED shown in FIG. 3(7) to the ECC mode decoder 31 and self-mode decoder32. As a result, the ECC mode decoder 31 resets a decode flag. On theother hand, the self-mode decoder 32, based on a high-level decodeterminating signal DEED, produces a high-level first self-refresh startsignal SRT₁ shown in FIG. 3(8) and feeds it to the self-refresh circuit22 and the OR gate 28.

[0110] This causes the internal state ST of the semiconductor storagedevice of the embodiment to be changed from its ECC decode state to itsself-refresh state SRST state. That is, the self-refresh circuit 22,since a first high-level self-refresh start signal SRT₁ has been fed,sets an oscillation frequency of a clock produced by the oscillator sothat the refresh period T_(R) becomes 15.6 μsec and produces aself-refresh signal φ SRF and feeds it to the row column address buffer8 and the command decoder 21. This causes the command decoder 21 toproduce a row activated signal φ RSA and to feed it to the row columnaddress buffer 8.

[0111] Therefore, the row column address buffer 8, when a firstself-refresh start signal SRT₁ is fed through the OR gate 28, based on acounter value RCT fed from the refresh counter 9, produces a row addressfor an ordinary self-refresh process and feeds it to a plurality of rowdecoders making up each of the row decoder groups 3 ₁ to 3 ₄ with timingwhen a row activated signals φ RSA is fed. Thereafter, in thesemiconductor storage device of the embodiment, refreshing operationsare performed at equal intervals on all word lines (4096 cycles) in arefresh period T_(R) of 15.6 μsec.

[0112] Next, to exit the self-refresh state SRST, for example, at thetime t₄, as shown in FIG. 3(3), the clock enable signal CKE is changedfrom its low to high level. This causes the self-mode decoder 32 tochange the first self-refresh start signal SRT₁ from its high to lowlevel as shown in FIG. 3(18) and feeds it to the self-refresh circuit 22and to the OR gate 28. Therefore, the self-refresh circuit 22, based ona low-level first self-refresh start signal SRT₁, stops the productionof the self-refresh signal φ SRF. As a result, the command decoder 21,since a self-refresh signal φ SRF is not fed from the self-refreshcircuit 22, stops the production of the row activated signals φ RSA. Byoperations described above, the internal state ST of the semiconductorstorage device of the embodiment, as shown in FIG. 3(5) and FIG. 4, ischanged from its self-refresh state SRST to its idle state IST.Moreover, in the semiconductor storage device described above, a reasonwhy a direct transition from the ECC decode state EDST to the idle stateIST does not occur is as follows. That is, since internal operations areperformed in synchronization with an internal clock CLK_(IN), if anerror correction caused by variations of an internal clock CLK_(IN)terminates earlier and then if transition of the internal state ST tothe idle state IST occurs without transition to its ordinaryself-refresh mode and remains left as it is, there is a risk that databeing stored in each of memories is destroyed.

[0113] (2) Case in which, after the semiconductor storage device hasbeen set to the ultra-low power consumption mode, the ultra-low powerconsumption mode exits in a state of the power-OFF state PFST (see FIG.5 and FIG. 6).

[0114] First, in the semiconductor storage device of the embodiment,after it is put in the ultra-low power consumption mode by a command SPCfed when the clock enable signal CKE is changed from its high to lowlevel, its internal state ST is changed sequentially from its idle stateIST through its ECC encode state EEST, burst self-refresh state BSST,power-OFF state PFST, and to power-ON state PNST, and then repeatedlyfrom its power-ON state to its burst self-refresh state BSST, from itsburst self-refresh state BSST to its power-OFF state PFST, and from itspower-OFF state PFST to its power-ON state PNST as shown in FIG. 6,which is the same as described in the above item (1) case and theirdescription is omitted accordingly.

[0115] Next, let it be assumed that, as shown in FIG. 5(3), at the timet₃ when the internal state ST of the semiconductor storage device of theembodiment is the power-OFF state PFST, in order to exit the ultra-lowpower consumption mode, the clock enable signal CKE is changed from itslow to high level. The self-mode decoder 32, in response to a change ofthe clock enable signal CKE from its low to high level, resets theultra-low power consumption flag and, at the same time, the ECC modedecoder 31, as shown in FIG. 5(19), resets the ultra-low powerconsumption flag SLPF. As a result, the timer 26, since it is measuringthe internal power source off time, in response to resetting of theultra-low power consumption flag SLPF, stops measurements of theinternal power source off time and feeds a high-level “internal powersource OFF signal” PEND shown in FIG. 5(6) to the self-refresh circuit22. Therefore, the self-refresh circuit 22, based on the high-level“internal power source OFF signal” PEND, in order to activate theinternal power source circuit 27, as shown in FIG. 5(13), changes the“internal power source OFF signal” GOFF from its high to low level andfeeds it to the internal power source circuit 27.

[0116] This causes the internal state ST of the semiconductor storagedevice of the embodiment to be changed, as shown by broken lines in FIG.5(5) and FIG. 6, from its power-OFF state PFST to its power-ON statePNST. That is, the internal power source circuit 27, since an “internalpower source OFF signal” GOFF changes from its high to low level, asshown in FIG. 5(15), starts a supply of an internal voltage to eachcomponent of the semiconductor storage device. Then, the internal powersource circuit 27, when having detected that a potential being monitoredhas reached a potential having a specified value, feeds the high-level“internal power source ON signal” GON shown in FIG. 5(14) to the ECCmode decoder 31 and to the self-mode decoder 32. Thus, though the“internal power source ON signal” GON has been changed from its low tohigh level, since the ultra-low power consumption flag has been reset,the self-mode decoder 32, as shown in FIG. 5(8), does not produce ahigh-level second self-refresh start signal SRT₂. On the other hand,since the “internal power source ON signal” GON has changed from its lowto high level and the ultra-low power consumption flag SLPF has beenreset, the ECC mode decoder 31 produces a high-level decode start signalDEST and feeds it to the ECC controller 23 and sets a decode flag.

[0117] This causes an internal state ST of the semiconductor storagedevice of the embodiment to be changed, as shown by broken lines in FIG.5(5) and in FIG. 6, from its power-ON state PNST to its ECC decode stateEDST. The internal state ST of the semiconductor storage devicethereafter, as in the above item (1) case, after having been changedfrom its ECC decode state EDST to its self-refresh state SRST, forexample, at the time t₄, as shown in FIG. 5(3), when the clock enablesignal CKE is changed from its low to high level, is changed to its idlestate IST.

[0118] (3) Case in which, after the semiconductor storage device hasbeen put in the ultra-low power consumption mode, the ultra-low powerconsumption mode exits in a state of the ECC encode state EEST (seeFIGS. 7 and 8).

[0119] First, in the semiconductor storage device of the embodiment,after it is put in the ultra-low power consumption mode by a command SECfed when the clock enable signal CKE is changed from its high to lowlevel, its internal state ST is changed from its idle state IST to itsECC encode state EEST, as shown in FIG. 8, which is the same asdescribed in the above item (1) case and their descriptions are omittedaccordingly.

[0120] Next, let it be assumed that, as shown in FIG. 7(3), at the timet₃ when the internal state ST of the semiconductor storage device of theembodiment is the ECC encode state EEST, in order to exit the ultra-lowpower consumption mode, the clock enable signal CKE is changed from itslow to high level. In response to a change of the clock enable signalCKE from its low to high level, the self-mode decoder 32 resets theultra-low power consumption flag and, at the same time, the ECC modedecoder 31, as shown in FIG. 7(9), resets the ultra-low powerconsumption flag SLPF. Then, the ECC controller 23, when paritycalculation to be performed on all memory cells making up each of memorycells 11 ₁ to 11 ₄ and writing of a parity region into each of thememory cells are terminated in the ECC 24, feeds an encode terminatingsignal ENED shown in FIG. 7(7) to the ECC mode decoder 31 and to theself-mode decoder 32. Therefore, the ECC mode decoder 31, when theencode terminating signal ENED is fed from the ECC controller 23, resetsthe encode flag. On the other hand, the self-mode decoder 32, since theultra-low power consumption flag is reset when the encode terminatingsignal ENED is fed from the ECC controller 23, produces a high-levelfirst self-refresh start signal SRT₁ shown in FIG. 7(8) and feeds it tothe self-refresh circuit 22 and to the OR gate 28.

[0121] This causes the internal state ST of the semiconductor storagedevice of the embodiment to be changed from its ECC encode state EEST toits self-refresh state SRST. The internal state ST of the semiconductorstorage device thereafter, as in the above item (1) case, after havingbeen changed from its ECC decode state EDST to its self-refresh stateSRST, at the time t₄, for example, as shown in FIG. 7(3), when the clockenable signal CKE is changed from its low to high level, is changed toits idle state IST.

[0122] (4) Case in which, after the semiconductor storage device hasbeen put in the ultra-low power consumption mode, the ultra-low powerconsumption mode exits in a state of the power-ON state PNST.

[0123] First, in the semiconductor storage device of the embodiment,after it is put in the ultra-low power consumption mode by a command SPCfed when the clock enable signal CKE is changed from its high to lowlevel, its internal state ST is changed sequentially from its idle stateIST through its ECC encode state EEST, burst self-refresh state BSST,power-OFF state PFST, and to power-ON state PNST, and then repeatedlyfrom its power-ON state to its burst self-refresh state BSST, from itsburst self-refresh state BSST to its power-OFF state PFST, and from itspower-OFF state PFST to its power-ON state PNST, which is the same asdescribed in the above item (1) case and their descriptions are omittedaccordingly.

[0124] Next, let it be assumed that, at the time when the internal stateST of the semiconductor storage device of the embodiment is the power-ONstate PNST, in order to exit the ultra-low power consumption mode, theclock enable signal CKE is changed from its low to high level. In thiscase, the internal state ST of the semiconductor storage device, afterhaving been changed to the power-ON state PNST, is sequentially changedto a one—time burst self-refresh state BSST, ECC encode state EEST, andself-refresh state SRST and, thereafter, as in the above item (1) case,when the clock enable signal CKE is changed from its low to high levelat a time, to the idle state IST.

[0125] Next, an external specification of the semiconductor storagedevice of the embodiment will be explained by referring to a timingchart shown in FIGS. 9 and 10. The diagonally shaded areas in FIGS. 9and 10 show that either of a high level or a low level of a signal canbe used for operations.

[0126] (A) External Specifications in Ultra-low Power Consumption Mode.

[0127] First, in synchronization with a rise of a clock CLK shown inFIG. 9(1), in order shown sequentially in FIG. 9(3) to FIG. 9(8), alow-level chip select signal /CS, low-level row address strobe signal/RAS, high-level column address strobe signal /CAS, low-level writeenable signal /WE, bank selection signal BS used to select any specifiedone out of banks 1 ₁ to 1 ₄, and address AD are provided at the time t₁.The low-level chip select signal /CS, low-level row address strobesignal /RAS, high-level column address strobe signal /CAS, and low-levelwrite enable signal /WE represent a command PCC used to issue aninstruction so that each of input and output lines being formed on eachof memory cell arrays 1 ₁ to 1 ₄ is put in a pre-charged state. Here,the pre-charged state denotes a state in which writing of data from anexternal and reading of data to the external are made possible in eachof memory cells mounted each corresponding to each of the input andoutput lines.

[0128] Next, at the time t₂ after pre-charged time t_(RP) or morepredetermined according to the specification has elapsed following thetime t₁, in synchronization with a rise of the clock CLK, the clockenable signal CKE shown in FIG. 9(2) is changed from its high to lowlevel and the low-level chip select signal /CS, high-level row addressstrobe signal /RAS, high-level column address strobe signal /CAS, andlow-level write enable signal /WE are provided in order shown in FIG.9(3) to FIG. 9 (6). The low-level chip select signal /CS, high-level rowaddress strobe signal /RAS, high-level column address strobe signal/CAS, and low-level write enable signal /WE represent a command SPC usedto make an instruction for setting of the ultra-low power consumptionmode. This causes the semiconductor storage device of the embodiment tobe put in the ultra-low power consumption mode and to initiate internaloperations described in a first half of the above item (1). Here, asupply of the command PCC, bank selection signal BS, and address AD isnot always required, however, it is necessary that such the command PCC,bank selecting signal BS, and address AD are fed earlier by time t_(RP)before the supply of the command SPC and the internal state has tocompletely be its idle state at a time of the supply of the command SPC.

[0129] Then, in order to exit the ultra-low power consumption mode, forexample, at the time t₃, the clock enable signal CKE shown in FIG. 9(2)is changed from its low to high level. As a result, the semiconductorstorage device of the embodiment, depending on an internal stateoccurring at the time when the clock enable signal CKE has changed fromits low to high level and according to procedures described in the aboveitems (1) to (4), starts exiting the ultra-low power consumption mode.Next, after having changed the clock enable signal CKE from its low tohigh level, before a predetermined time t_(SLT) elapses, for example, atthe time t₄, the clock enable signal CKE shown in FIG. 9(2) is changedfrom its high to low level and the address AD shown in FIG. 9(8) is fed.A reason why this process is performed is as follows. That is, asdescribed later, in order to change the internal state of thesemiconductor storage device of the embodiment from its self-refreshstate SRST to its idle state IST, it is necessary that, at the time t₅,the clock enable signal CKE is changed from its low to high level,however, before this change, the clock enable signal CKE has to bechanged from its low to high level without fail. However, a supply ofthe address AD is not always necessary.

[0130] Next, at the time t₃ after the predetermined time t_(SLE) haselapsed following the time t₄, the clock enable signal CKE shown in FIG.9(2) is changed from its low to high level. This causes the internalstate of the semiconductor storage device to be changed from itsself-refresh state SRST to its idle state IST according to proceduresdescribed in the above items (1) to (4). Here, the time t_(SLE) is, asdescribed in the above item (1), maximum time or more required forcorrection of errors caused by dispersion of the internal clock CLK_(IN)which is predetermined as its external specification when considerationsare given to the dispersion of the above internal clock CLK_(IN).

[0131] Next, at the time t₆ after the predetermined time t_(RC) haselapsed following the time t₅, in order shown in FIG. 9(3) to FIG. 9(6),the low-level chip select signal /CS, low-level row address strobesignal /RAS, low level column address strobe signal /CAS, and high-levelwrite enable signal /WE are provided. The low-level chip select signal/CS, low-level row address strobe signal /RAS, low-level column addressstrobe signal /CAS, and high-level write enable signal /WE represent acommand ORC used to issue an instruction for auto-refresh operations.Here, the auto-refresh operation is performed in a one-shot operationdesignating a refresh address by using the refresh counter 9. Moreover,if necessary, at the time t₇ after the predetermined time t_(RC) haselapsed following the time t₆, to activate each of banks 1 ₁ to 1 ₄, inorder shown in FIG. 9(3) to FIG. 9(6), the low-level chip select signal/CS, low-level row address strobe signal /RAS, high-level column addressstrobe signal /CAS, and high-level write enable signal /WE are provided.The low-level chip select signal /CS, low-level row address strobesignal /RAS, high-level column address strobe signal /CAS, andhigh-level write enable signal /WE represent a command BAC used toactivate each of banks 1 ₁ to 1 ₄.

[0132] (B) External Specifications of Ordinary Self-refresh Process.

[0133] First, at the time t₁, in synchronization with a rise of theclock CLK shown in FIG. 10(1), in order shown in FIG. 10(3) to FIG.10(1), the low-level chip select signal /CS, low-level row addressstrobe signal /RAS, high-level column address strobe signal /CAS, andlow-level write enable signal /WE, bank selection signal BS, and addressAD are fed. The low-level chip select signal /CS, low-level row addressstrobe signal /RAS, high-level column address strobe signal /CAS, andlow-level write enable signal /WE represent a command PCC describedabove.

[0134] Next, at the time t₂ after the predetermined time t_(RP) haselapsed following the time t₁, in order shown in FIG. 10(2), insynchronization with a clock CLK shown in FIG. 10(1), the clock enablesignal CKE is changed from its high to low level and, in order shown inFIG. 10(3) to FIG. 10(6), the low level chip select signal /CS,low-level row address strobe signal /RAS, low-level column addressstrobe signal /CA, and high-level write enable signal /WE are fed. Thelow-level chip select signal /CS, low-level row address strobe signal/RAS, low-level column address strobe signal /CAS, and high-level writeenable signal /WE represent a command SRC used to issue an instructionfor setting of an ordinary self-refresh mode. This causes thesemiconductor storage device of the embodiment to be put in the ordinaryself-refresh mode. Though a supply of the command PCC, bank selectionsignal BS, and address AD at the time t₁ is not always necessary, whenthese signals are fed, they have to be fed by the time t_(RF) before asupply of the command SRC and the internal state of the semiconductorstorage device has to be changed to a full idle state IST at the time ofthe supply of the command SRC. Then, to exit the ordinary self-refreshmode, for example, at a time t₃, the clock enable signal CKE shown inFIG. 10(2) is changed from its low to high level. This causes thesemiconductor storage device of the embodiment to start exiting theordinary self-refresh mode.

[0135] Next, to again put the semiconductor storage device into theordinary self-refresh mode, at the time t₅ when the clock CLK arrivesafter the time t₄, when the clock CLK (see FIG. 10(1)) rises immediatelybefore the lapse of the predetermined time t_(RC) following the time t₃,in synchronization with a rise of the clock CLK, the clock enable signalCKE is changed from its high to low level and in order shown in FIG.10(3) to FIG. 10(6), the low level chip select signal /CS, low level rowaddress strobe signal /RAS, low-level column address strobe signal /CAS,and high-level write enable signal /WE are fed. This causes thesemiconductor storage device of the embodiment to be put into theordinary self-refresh mode. Then, to again exit the ordinaryself-refresh mode, for example, at the time t₆, the clock enable signalCKK shown in FIG. 10(2) is changed from its low to high level. Thiscauses the semiconductor storage device of the embodiment to startexiting the ordinary self-refresh mode.

[0136] Thereafter, to perform auto-refresh operations, at the time t₇when the clock CLK arriving after the time t₇ when the clock CLK (seeFIG. 10(1)) rises immediately before the lapse of the predetermined timet_(RC) following the time t₆, rises and, in order shown in FIG. 10(3) toFIG. 10(6), the low-level chip select signal /CS, low-level row addressstrobe signal /RAS, low-level column address strobe signal /CA, andhigh-level write enable signal /WE, all of which represent a command ORCto issue an instruction for auto-refresh operations, are fed.

[0137] Thus, according to the semiconductor storage device of theembodiment, by putting an internal state of the semiconductor storagedevice into a state obtained by combining a state in an ultra-low powerconsumption mode in which an ECC encoder state EEST, burst self-refreshstate BSST, power-OFF state PFST, power-ON state PNST, and ECC decodestate EDST with an ordinary self-refresh state SRST are operated, agreat reduction in power consumption in a standby state can be achieved.

[0138] Here, effects of the power control employed in the semiconductorstorage device of the embodiment will be described by referring to FIG.11. In FIG. 11, a curve “a” represents a curve of a characteristic of acurrent for maintaining data to a real refreshing capability t_(REF) ina case where a direct current is 50 μA in the semiconductor storagedevice, while a curve “b” represents a curve of a characteristic of acurrent for maintaining data to a real refreshing capability t_(REF) ina case where an average amount of the direct current is 10 μA in thesemiconductor storage device of the embodiment. Since a real refreshingcapability t_(REF) of the semiconductor storage device of the embodimentis 64 msec, if any power controlling method is not employed, an amountof a current for maintaining data is about 200 μA as shown by point P₁in FIG. 11. Then, since the semiconductor storage device is put in theECC encode state and ECC decode state EDST, the apparent refreshing timeis extended to its maximum level that can be assured by thecharacteristic and, since an amount of an alternating current isreduced, the apparent refreshing capability t_(REF), as shown in FIG.11, is extended from the level at the point P₁ to point P₂ and an amountof the data maintaining current can be reduced to about 70 μA. Moreover,since the semiconductor storage device is put into the power-OFF statePFST, an amount of the direct current is reduced and, as a result, thedata maintaining current is reduced from an amount of the current at thepoint P₂ to that at the point P₃ being about 200 μA. The powercontrolling method employed in the semiconductor storage device of theembodiment can provide a greatest effect in portable electronic devicessuch as a portable cellular phone, PHS, or a like which is adapted toreturn to an ordinary operation state by a receipt of a signal when itis turned ON and while it is in a state waiting for an incoming signalfrom external.

[0139] It is apparent that the present invention is not limited to theabove embodiments but may be changed and modified without departing fromthe scope and spirit of the invention. For example, in the aboveembodiment, the clock CLK, internal clock CLK_(IN), and clock enablesignal CKE are active high and the chip select signal /CS, row addressstrobe signal /RAS, column address strobe signal /CAS and write enablesignal /WE are active low, however, all signals maybe active high orlow, or the clock CLK, internal clock CLK_(IN), row address strobesignal /RAS, column address strobe signal /CAS and write enable signal/WE may be active high. Moreover, in the above embodiment, in theinternal operations described in the above items (1) to (4), in order toexit the ultra-low power consumption mode, when the clock enable signalCKE is changed from its low to high level, the internal state, afterhaving been changed automatically to the self-refresh state SRST withoutfail, is changed to its idle state IST. However, the present inventionis not limited to this. That is, the semiconductor storage device may beconfigured so that, it is put, after its operation is set once to theordinary self-refresh mode and then the self-refresh mode exits, intothe idle state IST, however, the semiconductor storage device may be soconfigured that, by feeding a command SRC from an external, after havingput the semiconductor storage device once into an ordinary self-refreshmode, the ordinary self-refresh mode exits and transition to its idlestate IST occurs.

[0140] Also, in the above embodiment, the ECC mode decoder 31 and theself-mode decoder 32 are judged to have been put into the ultra-lowpower consumption mode or ordinary self-refresh mode when such thecombined signals as shown in FIG. 9(3) to FIG. 9(6) and in FIG. 10(3) toFIG. 10(6) are provided, however, types of signals or combinations ofsignals provided to the ECC mode decoder 31 and the self-decoder 32 maybe arbitrary. Examples of the above include address signals, datasignals, signals obtained by combining these signals with the above rowaddress strobe signal /RAS, or a like. That is, signals to be fed to theECC decoder 31 and self-rode decoder 32, so long as they are differentfrom noises and intentional signals, may be arbitrary.

[0141] Also, in the above embodiment, information about the internalstate ST of the semiconductor storage device cannot be obtained,however, the semiconductor storage device may be so configured that astate signal being set to be high in the ultra-low power consumptionmode is output from the input/output terminal DQ shown in FIG. 1. FIG.12 is a timing chart showing external specifications of thesemiconductor storage device employed when the above state signal isoutput. In FIG. 12, descriptions of portions having same waveforms orproviding same timing as in each of components in FIG. 9 are omitted. Inthis configuration, when the internal state of the semiconductor storagedevice is set to be the ultra-low power consumption mode, as shown inFIG. 12(9), a high-level state signal is output from the datainput/output terminal DQ. Therefore, by using this state signal, a usercan get information as to whether the internal state of thesemiconductor storage device is set to its ultra-low power consumptionmode. Therefore, a user, in order to exit the ultra-low powerconsumption mode, after having changed the clock enable signal CKE shownin FIG. 12(2) from its low to high level, by detecting that the statesignal shown in FIG. 12(9) has changed from its high to low level, forexample, at the time t₉, may feed a command ORC used to issue aninstruction for an auto-refresh process at the time t₆ or a command BACused to activate each of banks 1 ₁ to 1 ₄ at the time t₇. On the otherhand, the semiconductor storage device, in response to a change of theclock enable signal CKE shown in FIG. 12(2) from its low to high levelat the time t₃, after having charged its internal state ST to the ECCdecode operation state EDST, puts the data input/output terminal DQhaving output the state signal into a high impedance state. According toconfigurations described above, the user, after having exited theultra-low power consumption mode, can use straight the semiconductorstorage device without changing the internal state ST of thesemiconductor storage device to the self-refresh state SRST. Moreover,the semiconductor storage device may be so constructed that the statesignal can be output to an external with an exclusive pin.

[0142] Also, in the above embodiment, the ECC 24 operates insynchronization with the internal clock CLK_(IN), however, it may be soconstructed as to operate in synchronization with the clock CLK.Moreover, in the configuration described above, by obtaining informationabout a number of cycles required for the error correcting process inthe ECC 24, exact information as to whether or not the above errorcorrecting process has terminated can be gotten from an external and, asa result, the user can use the semiconductor storage device immediatelyafter the above error correcting process has been completed.

[0143] Also, in the above embodiment, the burst refresh process isperformed while the semiconductor storage device is put in its burstself-refresh state BSST, however, the refresh process may be performedin the same refresh period T_(R) as employed for an ordinaryself-refresh process. In this case, the internal power source off timebecomes shorter when compared with the embodiment and effects ofreducing a direct current become smaller, however, since one type of therefresh period T_(R) can be used, it is possible to simplifyconfigurations of the semiconductor storage device.

[0144] Also, in the above embodiment, after the ultra-low power sourcemode has been set, the internal state of the semiconductor storagedevice is first changed to its ECC encode state EEST and thensequentially through its burst self-refresh state BSST and power-OFFstate PFST, then to power-ON state PNST, however, the present inventionis not limited to the above. That is, the semiconductor storage devicemay be so constructed that, after the ultra-low power source mode hasbeen set, its internal state is first changed to its ECC encode stateEEST and then sequentially through its power-OFF state PEST, burstself-refresh state BSST, power-ON state PNST, and to its burstself-refresh state BSST and, thereafter, until the ultra-low powerconsumption mode exits, transition from its burst self-refresh state toits power-OFF state, from its power-OFF state to its power-ON state,from its power-ON state to its burst self-refresh state may be repeated.Since the refresh process is performed substantially in the ECC encodestate EEST, even if transition from the ECC encode state EEST to thepower-OFF state PFST occurs, data being stored in the memory cell is notdestroyed.

[0145] Also, in the above embodiment, in the ultra-low power consumptionmode, the ECC encode state EEST, burst self-refresh state BSST,power-OFF state PFST, power-ON state PNST, and ECC decode state EDST areprovided. However, the present invention is not limited to this. Forexample, in the semiconductor storage device having some large realrefreshing capability t_(REF), it may be so constructed that, in theultra-low power consumption mode, the burst self-refresh state BSST,power-OFF state PFST, and power-ON state PNST are provided. In thiscase, when the semiconductor storage device is put in the ultra-lowpower consumption mode, transition of its internal state from its idlestate IST to its burst self-refresh state BSST occurs and thentransition from its burst self-refresh state BSST to its power-OFF statePFST, from its power-OFF state PFST to its power-ON PNST, and from itspower-ON state PNST to its burst self-refresh state BSST is repeatedthereafter. Moreover, the above semiconductor storage device may be soconstructed that setting of and exiting from the above ultra-low powerconsumption mode is achieved by employing the same way of the settingand exiting as provided in the above embodiment or by mounting aregister adapted to select either of the above low power consumptionmode or the ordinary self-refresh mode inside of the command decoder 21and by selecting either of the modes depending on a value of theregister. Also, a method for transition according to the internal stateST of the semiconductor storage device to be employed when aninstruction for exiting is provided may be the same as in the aboveembodiment except that the ECC encode state EEST and ECC decode stateEDST do not exist. That is, if the semiconductor storage device is inthe burst self-refresh state BSST when the ultra-low power consumptionmode exits, transition to the self-refresh state SRST occurs. On theother hand, the semiconductor storage device is in the power-OFF statePFST when the ultra-low power consumption mode exits, transition to thepower-ON state PNST occurs and then transition to the self-refresh stateSRST occurs.

What is claimed is:
 1. A method for controlling power for asemiconductor storage device having a memory cell which must berefreshed to maintain data, comprising: a step of employing an ultra-lowpower consumption mode in which power control is exerted in a standbystate and in which a centralized refresh state, power-OFF state, andpower-ON state are provided, and wherein said memory cell is refreshedin a centralized manner in said centralized refresh state, an internalpower source circuit is partially turned OFF in said power-OFF state,and said internal power source circuit having been partially turned OFFis turned ON in said power-ON state.
 2. The method for controlling powerfor said semiconductor storage device according to claim 1, wherein, insaid ultra-low power consumption mode, an error correcting circuitencode state and an error correcting circuit decode state are providedand wherein, in said error correcting circuit encode state, anarithmetic operation is performed on parity bits by said errorcorrecting circuit to restore said memory cell whose maintainingcharacteristics are deteriorated and wherein, in said error correctingencode state, an error correction is made by said error correctingcircuit based on results from said arithmetic operations.
 3. The methodfor controlling power for said semiconductor storage device according toclaim 2, wherein said error correcting circuit operates insynchronization with a clock produced internally or fed from anexternal.
 4. The method for controlling power for the semiconductorstorage device according to claim 1, wherein a state signal indicatingthat said semiconductor storage device is internally put in saidultra-low power consumption mode is output to an external.
 5. The methodfor controlling power for the semiconductor storage device according toclaim 1, wherein said semiconductor storage device is configured tooperate in a self-refresh mode such that said memory cell isperiodically and automatically refreshed.
 6. The method for controllingpower for the semiconductor storage device according to claim 1,wherein, in said centralized refresh state, said refresh process isperformed on said memory cell in a period being shorter than that beingcorresponded to a maintaining characteristic of said memory cell.
 7. Themethod for controlling power for the semiconductor storage deviceaccording to claim 1, wherein, in said power-OFF state, all powersources other than paired poles in said internal power source circuitare turned OFF.
 8. The method for controlling power for thesemiconductor storage device according to claim 1, wherein, in saidpower-OFF state, leak paths of peripheral circuits of a memory cellarray made up of a plurality of said memory cells are interrupted. 9.The method for controlling power for the semiconductor storage deviceaccording to claim 1, wherein transition to said centralized refreshstate occurs when instructions for said semiconductor storage device tobe put in said ultra-low power consumption mode are provided and thentransition from said centralized refresh state to said power-OFF state,from said power-OFF state to said power-ON state, and from said power-ONstate to said centralized state are repeated.
 10. The method forcontrolling power for the semiconductor according to claim 1, wherein,in said ultra-low power consumption mode, if said semiconductor storagedevice is put in said centralized refresh state when instructions forexiting of said ultra-low power consumption mode are provided,transition occurs to a self-refresh state in which said memory cell isrefreshed in a period corresponding to a maintaining characteristic ofsaid memory cell.
 11. The method for controlling power for thesemiconductor according to claim 1, wherein, in said ultra-low powerconsumption mode, if said semiconductor storage device is put in saidpower-OFF state when instructions for exiting said ultra-low powerconsumption mode are provided, transition occurs to a self-refresh statein which said memory cell is refreshed in a period corresponding to amaintaining characteristic of said memory cell.
 12. The method forcontrolling power for the semiconductor according to claim 2, wherein,when instructions for said semiconductor storage device to be put insaid ultra-low power consumption mode are provided, transition to saiderror correcting circuit encode state and to said centralized refreshstate sequentially occur and, until instructions for exiting saidultra-low power consumption mode are provided, transition from saidcentralized refresh state to said power-OFF state, from said power-OFFstate to said power-ON state, and from said power-ON state to saidcentralized refresh state are repeated.
 13. The method for controllingpower for the semiconductor storage device according to claim 2,wherein, when instructions for said semiconductor storage device to beput in said ultra-low power consumption mode are provided, transition tosaid error correcting encode state, to said power-OFF state, and to saidcentralized refresh state sequentially occurs and, until instructionsfor exiting said ultra-low power consumption mode are provided,transition from said centralized refresh state to said power-OFF state,from said power-OFF state to said power-ON state, and from said power-ONstate to said centralized refresh state are repeated.
 14. The method forcontrolling power for the semiconductor storage device according toclaim 2, wherein, in said ultra-low power consumption mode, if saidsemiconductor storage device is put in said centralized refresh statewhen said ultra-low power consumption mode exits, transition to saiderror correcting circuit decode state occurs and then transition occursto a self-refresh state in which said memory cell is refreshed in aperiod corresponding to a maintaining characteristic of said memorycell.
 15. The method for controlling power for the semiconductor storagedevice according to claim 2, wherein, in said ultra-low powerconsumption mode, if said semiconductor storage device is put in saidpower-OFF state when instructions for exiting said ultra-low powerconsumption mode are provided, transition to said power-ON state and tosaid error correcting circuit decode state sequentially occurs and thentransition occurs to a self-refresh state in which said memory cell isrefreshed in a period corresponding to a maintaining characteristic ofsaid memory cell.
 16. The method for controlling power for thesemiconductor storage device according to claim 2, wherein, in saidultra-low power consumption mode, if said semiconductor storage deviceis put in said error correcting circuit encode state when instructionsfor exiting said ultra-low power consumption mode are provided, aftertermination of said error correcting circuit encode state, transitionoccurs to a self-refresh state in which said memory cell is refreshed ina period corresponding to a maintaining characteristic of said memorycell.
 17. The method for controlling power for the semiconductor storagedevice according to claim 1, wherein instructions are provided to putsaid semiconductor storage device into said ultra-low power consumptionmode by a first change occurring in a specified signal fed from anexternal and to exit said ultra-low power consumption mode by a secondchange occurring in said specified signal.
 18. The method forcontrolling power for the semiconductor storage device according toclaim 17, wherein, after instructions have been provided for exitingsaid ultra-low power consumption mode, instructions are provided fortransition of an internal state of said semiconductor storage device toan idle state where no operation is performed again by said secondchange occurring in said specified signal.
 19. The method forcontrolling power for the semiconductor storage device according toclaim 18, wherein, after having said specified signal produce saidsecond change in order to give instructions for exiting said ultra-lowpower consumption mode, when maximum time or more required for errorcorrections in said error correcting circuit decode state has elapsed,said second change is produced in said specified signal used to giveinstructions for exiting an internal state of said semiconductor storagedevice to said idle state.
 20. A semiconductor storage device having amemory cell which must be refreshed to maintain data, comprising: aself-refresh executing unit to refresh said memory cell; an internalpower source circuit to provide power to each of components; and acontroller, when instructions are provided for operations in anultra-low power consumption mode in order to exert power control in astandby state, to have said self-refresh executing unit execute refreshoperations in a centralized refresh state in which a centralized refreshprocess is performed on said memory cell, in a power-OFF state in whichsaid internal power source circuit is partially turned OFF, and in apower-ON state in which said internal power source circuit having beenpartially turned OFF is turned ON.
 21. The semiconductor storage deviceaccording to claim 20, further comprising an error correcting circuitused to perform arithmetic operations on parity bits to restore saidmemory cell whose maintaining characteristics are deteriorated and tomake error corrections based on results from said arithmetic operationsand wherein said controller executes operations in an error correctingcircuit encode state to have said error correcting circuit perform saidarithmetic operations and in an error correcting circuit decode state tohave said error correcting circuit make said error correction.
 22. Thesemiconductor storage device according to claim 21, wherein said errorcorrecting circuit operates in synchronization with a clock occurringinternally or being fed from an external.
 23. The semiconductor storagedevice according to claim 20, wherein said controller outputs a statesignal indicating that said semiconductor storage device is internallyput in said ultra-low power consumption mode.
 24. The semiconductorstorage device according to claim 20, wherein a self-refresh mode isused such that said memory cell is periodically and automaticallyrefreshed.
 25. The semiconductor storage device according to claim 20,wherein said controller has, in said centralized refresh state, saidrefresh executing unit perform said refresh process in a period beingshorter than that corresponding to a maintaining characteristic of saidmemory cell.
 26. The semiconductor storage device according to claim 20,wherein said controller, in said power-OFF state, turns OFF all powersources other than paired poles in said internal power source circuit.27. The semiconductor storage device according to claim 20, wherein saidcontroller, in said power-OFF state, interrupts a leak path ofperipheral circuits of a memory array made up of a plurality of saidmemory cells.
 28. The semiconductor storage device according to claim20, wherein said controller, when instructions are provided foroperations in said ultra-low power consumption mode, changes an internalstate of said semiconductor storage device to said centralized refreshstate and, until instructions for exiting said ultra-low powerconsumption mode are provided, repeats transition from said centralizedrefresh state to said power-OFF state, from said power-OFF state to saidpower-ON state, and from said power-ON state to said centralized refreshstate.
 29. The semiconductor storage device according to claim 20,wherein said controller, in said ultra-low power consumption state, ifsaid semiconductor storage device is put in said centralized refreshstate when instructions for exiting said ultra-low power consumptionstate are provided, induces occurrence of transition of an internalstate of said semiconductor storage device to a self-refresh state inwhich a refresh process is performed on said memory cell in a periodcorresponding to a maintaining characteristic of said memory cell. 30.The semiconductor storage device according to claim 20, wherein saidcontroller, in said ultra-low power consumption mode, if saidsemiconductor storage device is put in said power-OFF state wheninstructions for exiting said ultra-low power consumption mode areprovided, changes an internal state of said semiconductor storage deviceto said power-ON state and then induces occurrence of transition to aself-refresh state in which a refresh process is performed on saidmemory cell in a period corresponding to a maintaining characteristic ofsaid memory cell.
 31. The semiconductor storage device according toclaim 21, wherein said controller, when instructions for operations insaid ultra-low power consumption are provided, sequentially changes aninternal state of said semiconductor storage device to said errorcorrecting circuit encode state and to said centralized refresh stateand, until instructions for exiting said ultra-low power consumption areprovided, repeats transition from said centralized refresh state to saidpower-OFF state, from said power-OFF state to said power-ON state, andfrom said power-ON state to said centralized refresh state.
 32. Thesemiconductor storage device according to claim 21, wherein saidcontroller, when instructions for operations in said ultra-low powerconsumption are provided, sequentially changes an internal state of saidsemiconductor storage device to said error correcting circuit encodestate, to said power-OFF state, and to said centralized refresh stateand, until instructions for exiting said ultra-low power consumption areprovided, repeats transition from said centralized refresh state to saidpower-OFF state, from said power-OFF state to said power-ON state, andfrom said power-ON state to said centralized refresh state.
 33. Thesemiconductor storage device according to claim 21, wherein saidcontroller, in said ultra-low power consumption mode, if saidsemiconductor storage device is put in said centralized refresh statewhen instructions for exiting said ultra-low power consumption mode areprovided, changes an internal state of said semiconductor storage deviceto said error correcting circuit decode state and then inducesoccurrence of transition of an internal state of said semiconductorstorage device to a self-refresh state in which said memory cell isrefreshed in a period corresponding to a maintaining characteristic ofsaid memory cell.
 34. The semiconductor storage device according toclaim 21, wherein said controller, in said ultra-low power consumptionmode, if said semiconductor storage device is put in said power-OFFstate when instructions for exiting said ultra-low power consumptionmode are provided, changes an internal state of said semiconductorstorage device to said power-ON state and to said error correctingcircuit decode state and then induces occurrence of transition of aninternal state of said semiconductor storage device to a self-refreshstate in which a refresh process is performed on said memory cell in aperiod corresponding to a maintaining characteristic of said memorycell.
 35. The semiconductor storage device according to claim 21,wherein said controller, in said ultra-low power consumption mode, ifsaid semiconductor storage device is put in said error correctingcircuit encode state when instructions for exiting said ultra-low powerconsumption mode are provided and after said error correcting circuitencode state has been terminated, induces occurrence of transition of aninternal state of said semiconductor storage device to a self-refreshstate in which a refresh process is performed on said memory cell in aperiod corresponding to a maintaining characteristic of said memorycell.
 36. The semiconductor storage device according to claim 20,wherein instructions for operations in said ultra-low power consumptionmode are provided by a first change occurring in said specified signaland instructions for exiting said ultra-low power consumption mode areprovided by a second change occurring in said specified signal.
 37. Thesemiconductor storage device according to claim 36, wherein, after saidultra-low power consumption mode has exited, instructions for transitionof an internal state of said semiconductor storage device into an idlestate in which no operation is performed are provided by said secondchange again occurring in said specified signal.
 38. The semiconductorstorage device according to claim 37, wherein, after said second changehas occurred in said specified signal which are used to provideinstructions for exiting said ultra-low power consumption mode and whenmaximum time or more required for error correction in said errorcorrecting circuit decode state has elapsed, said second change isproduced in said specified signal to provide instructions for transferof an internal state of said semiconductor storage device to said idlestate.
 39. A semiconductor storage device having a memory cell whichmust be refreshed to maintain data, comprising: a self-refresh executingmeans to refresh said memory cell; an internal power source circuit toprovide power to each of components; and a controlling means, wheninstructions are provided for operations in an ultra-low powerconsumption mode in order to exert power control in a standby state, tohave said self-refresh executing means execute refresh operations in acentralized refresh state in which a centralized refresh process isperformed on said memory cell, an a power-OFF state in which saidinternal power source circuit is partially turned OFF, and in a power-ONstate in which said internal power source circuit having been partiallyturned OFF is turned ON.
 40. The semiconductor storage device accordingto claim 39, further comprising an error correcting circuit used toperform arithmetic operations on parity bits to restore said memory cellwhose maintaining characteristics are deteriorated and to make errorcorrections based on results from said arithmetic operations and whereinsaid controlling means executes operations in an error correctingcircuit encode state to have said error correcting circuit perform saidarithmetic operations and in an error correcting circuit decode state tohave said error correcting circuit make said error correction.
 41. Thesemiconductor storage device according to claim 40, wherein said errorcorrecting circuit operates in synchronization with a clock occurringinternally or being fed from an external.
 42. The semiconductor storagedevice according to claim 39, wherein said controlling means outputs astate signal indicating that said semiconductor storage device isinternally put in said ultra-low power consumption mode.
 43. Thesemiconductor storage device according to claim 39, wherein aself-refresh mode is used such that said memory cell is periodically andautomatically refreshed.
 44. The semiconductor storage device accordingto claim 39, wherein said controlling means has, in said centralizedrefresh state, said refresh executing means perform said refresh processin a period being shorter than that corresponding to a maintainingcharacteristic of said memory cell.
 45. The semiconductor storage deviceaccording to claim 39, wherein said controlling means, in said power-OFFstate, turns OFF all power sources other than paired poles in saidinternal power source circuit.
 46. The semiconductor storage deviceaccording to claim 39, wherein said controlling means, in said power-OFFstate, interrupts a leak path of peripheral circuits of a memory arraymade up of a plurality of said memory cells.
 47. The semiconductorstorage device according to claim 39, wherein said controlling means,when instructions are provided for operations in said ultra-low powerconsumption mode, changes an internal state of said semiconductorstorage device to said centralized refresh state and, until instructionsfor exiting said ultra-low power consumption mode are provided, repeatstransition from said centralized refresh state to said power-OFF state,from said power-OFF state to said power-ON state, and from said power-ONstate to said centralized refresh state.